1. Field of Invention
The present invention is related mixed-signal integrated circuits and in particular the trimming digital to analog converters comprising voltage, current, time and frequency.
2. Description of Related Art
The trend in microelectronics is the continued creation of smaller and smaller devices, wherein as the devices become smaller, variations in the fringe of each shape of a device become a larger portion of the of the performance characteristics of the device and cause variations in the performance of a circuit dependent on the device. This is particularly important in circuits that convert from one signal domain to another where precision in the conversion is required such as digital to analog converters. The variation in the output signal compared to an ideal response is known as a differential non-linearity (DNL) of the converted output signal.
There are several approaches to correcting for manufacturing process variations in the production of semiconductor circuits, which attempt to correct for variations producing analog values. In FIG. 1A is shown a binary weighted trim DAC of prior art in which an analog signal (current) is created that starts with a current generator producing 84% of the required analog signal and selectable additional current to attain 100% of the value of the analog signal that is required. Selection is by digitally controlling switches, which allow the current from the additional circuits to be added to the current of the current generator producing 84% of the required current. FIG. 1B is an approach of the prior art that is similar to that of FIG. 1A with the exception that each element of the selectable additional current has N elements of the minimum selectable current of the circuit of FIG. 1A. FIG. 1C of prior art is similar to FIG. 1A, but uses capacitance as the parameter that is being totalized to 100%. Another example of prior art is shown in FIG. 1D, where selectable elements of a voltage divider are used to create a voltage that is commensurate with the digital input. It should be noted that the values of the switchable elements are double the previous element, e.g. 1, 2, 4, 8, etc. In FIG. 1E is a resistor voltage divider stack where each resistor is of the same value and a series of switches between each resistor is used to select the desired voltage. In the general, the circuits of FIG. 1A through 1E form a DAC as a digital control in generating an analog value. These methods can provide useful results with the potential drag on conversion time needed to determine values created at the time of calibration.
U.S. Pat. No. 7,277,350 (Huckaby et al.) is directed to a method and apparatus for adjusting trim settings for internally generated voltages comparing a target digital value to a present digital value to introduce a trim value. U.S. Pat. No. 6,703,955 (Otani et al.) is directed to a code in which resistor selection produces an output voltage that represents an input voltage. In U.S. Pat. No. 6,504,394 (Ohlhoff), a circuit is directed to trimming reference voltages where the reference voltages are compared to an external comparison voltage. U.S. Pat. No. 7,193,548 B2 (Kaplan) is directed to a digital-to-analog converter mismatch shaper using a delta sigma modulator that has analog signal processing components. In U.S. Pat. No. 7,675,792 B2 (Bedeschi et al.), a voltage and a current reference generator are directed to a control stage couple to the reference generator stage to adjust trimmable parameters. U.S. Pat. No. 7,642,852 B2 (Chandra et al.), is directed to a method and apparatus for trimming values of load resistors to reduce variation in a common mode feedback loop of an operational amplifier. U.S. Pat. No. 7,433,790 (Anderson et al.) is directed to trimming of a reference controlled by an algorithm executed by logic circuitry.
U.S. Pat. No. 7,411,380 B2 (Chang et al.) is directed to a non-linear compensation circuit for compensating non-linear effects of a voltage reference. U.S. Pat. No. 7,362,247 B2 (Arias et al.) is directed to digital correction of a multi-bit ADAC non-linearities for error feedback. U.S. Pat. No. 7,019,585 B1 (Wilson et al.) is directed to a voltage trim circuit using an operational amplifier, a transistor, a voltage divider and a bias current circuit. In U.S. Pat. No. 7,002,496 B2 (Kuyel) a system and method is directed to calibrating a digital-to-analog converter comprising a memory and logic circuitry for performing arithmetic operations. U.S. Pat. No. 6,909,642 B2 (Lehmann et al.) is directed to integrated circuit chips capable and the method thereof for self-adjusting the internal voltage the integrated circuit chip. U.S. Pat. No. 6,906,581 B2 (Kang et al.) is directed to a fast start low-voltage bandgap voltage reference circuit using a first current generator with a positive temperature coefficient and second current generator with a negative temperature coefficient. IN U.S. Pat. No. 6,897,794 B2 (Kuyel et al.) a system and method is directed to calibrating a digital-to analog converter that makes use of a resistor string. In U.S. Pat. No. 6,671,221 B2 (Beer et al.) a circuit is directed to trimming the frequency of an oscillator.
U.S. Pat. No. 6,556,161 B2 (Nuijten) is directed to a multi-bit digital-to-analog converter comprising a plurality of conversion elements that are selected by dynamic element matching. In U.S. Pat. No. 6,329,804 B1 (Mercer) a method and apparatus is directed to trimming the level and slope in a voltage reference using a current switching DAC. U.S. Pat. No. 6,157,245 (Rincon-Mora) is directed to a curvature corrected bandgap reference voltage circuit independent of temperature operation of the circuit. U.S. Pat. No. 5,666,118 (Gersbach) is directed to a method of self-calibration for a segmented digital-to-analog converter comprising an output consisting of a voltage step and a trim value. U.S. Pat. No. 5,352,973 (Audy) is directed to an output curvature correction for a bandgap reference circuit that exhibits a temperature dependent output. In Das, T. et al.; inventor identified, “Self-calibration of input-match in RF front-end circuitry” IEEE Transactions, vol 52, no. 12, pp. 821-825, December 2005 is directed to a technique to ascertain an input match frequency of a circuit by using a built-in-self-test structure, determines the frequency interval that needs to be shifted and feeds back a digital word to correct the input mismatch.